The goal of the second phase of the lpnTPM project was to design a PCB for the final device. According to the conducted research, in our opinion it is too early for decisions related to the choice of base MCU, hence the electronics design phase had to be postponed to a later stage. We have however made some good progress in collecting the knowledge base that will enable us in the future, to go smoothly through the design process.
General aspects of TPM hardware design
Modern TPM devices are mainly designed and produced by motherboard vendors and vary greatly in the mechanical design aspect. There is no single standard for describing the size, connector type, or other physical properties of the module. In addition, vendors may use different connectors for the different interfaces their TPM module support (LPC / SPI).
TCG leaves this aspect to motherboard makers to let them create the solution that best fits their ideology of hardware development.
The photo below illustrates the two main trends in mechanical design that allows adapting to the limited space in computer cases.
We provide our database of different TPM pinouts of different vendors. We consider a double row IDC connector with 2.54 mm pitch as the main connector of choice for motherboard manufacturers but here the similarities end. Pin count, as well as pinout itself, differs from vendor to vendor.
We’ve collected the most common TPM modules pinouts. and discovered some similarities and differences between those. You can find some final thoughts on that topic in the summary of pinout related documentation.
Modular design concept
As we design a universal device that will work with mainboards of various vendors – we decided to focus on a modular design structure, separating the main PCB of the microcontroller from the converter board.
For connector type between a converter and mainboard, we found the following mechanical designs to be further investigated and implemented.
- Mini IDC 2×5 socket 1mm pitch
- Snap-in connectors (similar to the Raspberry Pi 4 Compute module) link
- M.2 connector type link
At the current state of development, we are using STM32L476 – the same as in the reference ms-tpm-20-ref implementation. Before final selection of the microprocessor, we have to be absolutely sure, that it will handle the full requirements of our software design goals.
Just after successful SPI communication, we are planning to create a set of extensive test cases of TPM executed commands (using tpm2-tools), to catch all of the potential CPU speed and memory size-related problems.
We have prepared some requirements for communication interfaces. It is still yet to decide if we want to use some kind of LPC bus controller emulation or to accomplish the communication using a dedicated converter IC or custom FPGA design.
Final tests on the actual hardware will confirm our early findings on memory usage of the reference ms-tpm-20-ref implementation. Right now static memory analyzers tell us, that we almost exceeded the STM32L476 limitations.
As it turns out the actual throughput of LPC bus is 2.47MB – Table 18: Peripheral Initiated Memory Read Cycle so in the case of bit-banging of LPC interface, we should probably choose some faster microcontroller like for example STM32G4 Series.
We have evaluated all of the most important aspects of the target hardware design. Due to the complexity of the solution, the hardware requirements are still not set in stone until we implement the full TPM feature set on the development board. Manufacturing hardware right now could be counter-productive That is why we have decided to continue development on the Nucleo L476RG board and postpone the target hardware manufacturing until we are certain about the final requirements of this application.
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